1. Field of the Invention
The present invention relates to a chip packaging technology, and more particularly, to a package substrate and a chip package structure employing such the package substrate.
2. Description of Related Art
Package substrates are a packaging component often used in current semiconductor packaging technology. The package substrate includes a plurality of patterned conductive layers and a plurality of dielectric layers alternatingly laminated with each other, and the adjacent layers can be electrically connected by the conductive vias. The two outmost patterned conductive layers respectively on the opposite surfaces of the package substrate include a plurality of pads. The package substrate further includes two solder-mask layers that cover the two outmost patterned conductive layers, respectively. These solder-mask layers have a plurality of openings. The openings expose portions of the pads, respectively, to define bonding areas of the pads.
A chip may be assembled onto the package substrate by flip-chip bonding or wire bonding to form a chip package structure. In addition, the package substrate may further be assembled to an external component (e.g. a printed circuit board) via solder balls disposed on the pads of the package substrate. However, when the bonding area of the pad is defined by the opening of the solder-mask layer, i.e. the pad is of a solder-mask-defined (SMD) type, the solder ball contacts only portion of the pad. Therefore, the solder ball may not be stably adhered onto the pad, thus degrading the reliability of the chip package structure. In addition, fabrication process needs to vary based on the structure requirements of different package substrates.